Top 15 List of 2023 IEEE based MTech VLSI Projects | Verilog
mtech vlsi projects

We provide MTech VLSI Projects and support students till the final submission of the project. We explain the IEEE base paper with the algorithm used in it. We provide review-wise progress in the implementation of the project.


1 A Design Implementation and Comparative Analysis of Advanced Encryption Standard (AES) Algorithm on FPGA
2 Design and Verification of High-Speed Radix-2 Butterfly FFT Module for DSP Applications
3 VLSI Implementation of Reed Solomon Codes
4 Design Analysis of Wallace Tree-based Multiplier using Approximate Full Adder and Kogge Stone Adder
5 VLSI Design of a Squaring Architecture Based on Yavadunam Sutra of Vedic Mathematics
6 The Method Of Low Power, High Performance, And Area Efficient Address Decoder Design For SRAM
7 Low Power Design of 4-bit Simultaneous Counter using Digital Switching Circuits for Low Range Counting Applications
8 Area-Efficient Pipelined VLSI Architecture for Polar Decoder
9 Implementation of Efficient Modulo 2n Adders for Cryptographic Applications
10 Design of Modified Dual-CLCG Algorithm for Pseudo-Random Bit Generator
11 Area and Power Efficient 64-Bit Booth Multiplier
12 A Low-Cost High Performance VLSI Architecture for Image Scaling in Multimedia Applications
13 VLSI Architecture for High-Performance Wallace Tree Encoder
14 Efficient Operand Divided Hybrid Adder for Error Tolerant Applications
15 Efficient Hardware Implementation of 2D Convolution on FPGA for Image Processing Application
16 Hardware-Efficient Post-processing Architectures for True Random Number Generators
17 Error Detection and Correction in SRAM Emulated TCAMs
18 Low-Power High-Accuracy Approximate Multiplier Using Approximate High-Order Compressors
19 RandShift: An Energy-Efficient Fault-Tolerant Method in Secure Nonvolatile Main Memory
Scroll to Top