List of 2023 VLSI mini projects | Verilog | Hyderabad

We provide VLSI mini projects for ECE with the fundamentals of Hardware Description Languages like VHDL/VERILOG. We offer you a detailed understanding of the HDL language modules, tasks and functions.

Written for project algorithm and make you build up your own code for model examples.

1. Vectored Implementation of Hierarchical 22n QAM
2. Normalized Subband Adaptive Filtering Algorithm with Reduced Computational Complexity
3. Low-Power Architecture for the Design of a One-Dimensional Median Filter
4 Area-Delay Efficient Binary Adders in QCA
5 Input Vector Monitoring Concurrent BIST Architecture Using SRAM Cells
6 Data encoding techniques for reducing energy Consumption in network-on-chip
7 Area-Delay-Power Efficient Fixed-Point LMS Adaptive Filter With Low Adaptation-Delay
8 Reverse Converter Design via Parallel-Prefix Adders: Novel Components, Methodology, and Implementations
9 Low-Complexity Low-Latency Architecture for Matching of Data Encoded With Hard Systematic Error-Correcting Codes
10 Critical-Path Analysis and Low-Complexity Implementation of the LMS Adaptive Algorithm
11 Aging-Aware Reliable Multiplier Design With Adaptive Hold Logic
12 Efficient FPGA Implementation of Address Generator for WiMAX Deinterleaver
13 VLSI implementation of a low cost and high quality image scaling processor
14 An Efficient Constant Multiplier Architecture Based on Vertical-Horizontal Binary Common Sub-expression Elimination Algorithm for Reconfigurable FIR Filter Synthesis
15 Low-cost and high-speed hardware implementation of contrast-preserving image dynamic range compression for full-HD video enhancement.
16 Low-Power and Area-Efficient Shift Register Using Pulsed Latches.
17 FPGA Implementation and Evaluation of Discrete-time Chaotic Generators Circuits
18 Result-Biased Distributed-Arithmetic-Based  Filter Architectures for Approximately Computing the DWT
19 Reconfigurable Filter Bank With Complete Control Over Sub band Bandwidths for Multi standard Wireless Communication Receivers
20 Efficient Parallel Architecture for Linear Feedback Shift Registers
21 Efficient VLSI Architecture for Decimation-in-Time Fast Fourier Transform of Real-Valued Data
22 A Fully-Integrated Low-Dropout Regulator with Full-Spectrum Power Supply Rejection
23 Design and Analysis of an Adaptively Biased Low Dropout Regulator Using Enhanced Current Mirror Buffer
24 Design of Improved Performance Voltage Controlled Ring Oscillator
25 Analysis and Design of Dual-Mode CMOS LC VCOs
26 Design of ATM (Automated Teller Machine)
27 VLSI based robust router architecture
28 Calculation of LFSR Seed and Polynomial Pair for BIST Applications
29 Design of floating point arithmetic unit using verilog
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