We provide VLSI mini projects for ECE with the fundamentals of Hardware Description Languages like VHDL/VERILOG. We offer you a detailed understanding of the HDL language modules, tasks and functions.
Written for project algorithm and make you build up your own code for model examples.
|VLSI MINI PROJECT LIST
|Vectored Implementation of Hierarchical 22n QAM
|Normalized Subband Adaptive Filtering Algorithm with Reduced Computational Complexity
|Low-Power Architecture for the Design of a One-Dimensional Median Filter
|Area-Delay Efficient Binary Adders in QCA
|Input Vector Monitoring Concurrent BIST Architecture Using SRAM Cells
|Data encoding techniques for reducing energy Consumption in network-on-chip
|Area-Delay-Power Efficient Fixed-Point LMS Adaptive Filter With Low Adaptation-Delay
|Reverse Converter Design via Parallel-Prefix Adders: Novel Components, Methodology, and Implementations
|Low-Complexity Low-Latency Architecture for Matching of Data Encoded With Hard Systematic Error-Correcting Codes
|Critical-Path Analysis and Low-Complexity Implementation of the LMS Adaptive Algorithm
|Aging-Aware Reliable Multiplier Design With Adaptive Hold Logic
|Efficient FPGA Implementation of Address Generator for WiMAX Deinterleaver
|VLSI implementation of a low cost and high quality image scaling processor
|An Efficient Constant Multiplier Architecture Based on Vertical-Horizontal Binary Common Sub-expression Elimination Algorithm for Reconfigurable FIR Filter Synthesis
|Low-cost and high-speed hardware implementation of contrast-preserving image dynamic range compression for full-HD video enhancement.
|Low-Power and Area-Efficient Shift Register Using Pulsed Latches.
|FPGA Implementation and Evaluation of Discrete-time Chaotic Generators Circuits
|Result-Biased Distributed-Arithmetic-Based Filter Architectures for Approximately Computing the DWT
|Reconfigurable Filter Bank With Complete Control Over Sub band Bandwidths for Multi standard Wireless Communication Receivers
|Efficient Parallel Architecture for Linear Feedback Shift Registers
|Efficient VLSI Architecture for Decimation-in-Time Fast Fourier Transform of Real-Valued Data
|A Fully-Integrated Low-Dropout Regulator with Full-Spectrum Power Supply Rejection
|Design and Analysis of an Adaptively Biased Low Dropout Regulator Using Enhanced Current Mirror Buffer
|Design of Improved Performance Voltage Controlled Ring Oscillator
|Analysis and Design of Dual-Mode CMOS LC VCOs
|Design of ATM (Automated Teller Machine)
|VLSI based robust router architecture
|Calculation of LFSR Seed and Polynomial Pair for BIST Applications
|Design of floating point arithmetic unit using verilog